Hardware acceleration involves the use of hardware to perform some functions more efficiently than software executing on a general-purpose CPU. A hardware accelerator is special-purpose hardware designed to implement hardware acceleration for some application. Example applications include neural networks, video encoding, decoding, transcoding, etc., network data processing, and the like. Software executing on the computing system interacts with the hardware accelerator through various drivers and libraries. One type of hardware accelerator includes a programmable device and associated circuitry. For example, the programmable device can be a field programmable gate array (FPGA) or a system-on-chip (SOC) that includes FPGA programmable logic among other components, such as a processing system, data processing engine (DPE) array, network-on-chip (NOC), and the like.
Users employ development environments to design applications for hardware accelerators. Users interact with a development environment to define an application using software programming languages and/or register transfer level (RTL) descriptions of circuits. Users then interact with the development environment to compile the application source code and generate implementation file(s) used to configure a target platform (e.g., a hardware accelerator in a computer system). The compilation process includes several steps, some of which involve placing compute units (referred to herein as “kernels”) designed by the user in programmable logic of a programmable device, and connecting memory interfaces of the kernels to particular channels (referred to herein as “banks”) of memory on the hardware accelerator. Inefficient placement of kernels in the programmable logic can lead to routing congestion, inefficient use of the memory, and ultimately poor quality of results (QOR).